1. Field of the Invention
This invention relates to a constant current driving circuit which is capable of performing constant current driving of a load without being influenced by power supply variation, temperature variation and process variation.
2. Prior Art
Conventionally, to transfer signals between internal circuits of two IC chips, an off-chip driver is sometimes employed. Such an off-chip driver includes a constant current driving circuit as shown in FIG. 1, which uses current mirror circuits, and is free from the influence of power supply variation, temperature variation and process variation.
The conventional constant current driving circuit has a reference current source circuit formed of an operational amplifier OP which has an inverting input terminal thereof supplied with reference voltage VREF, a PMOS transistor P21 driven by an output from the operational amplifier OP, and a resistance R connected to a drain terminal A of the PMOS transistor P21. In the reference current source circuit, the output from the operational amplifier OP is negatively fed back by the PMOS transistor P21 such that voltage at the terminal A is always equal to the reference voltage VREF. Therefore, provided that the reference voltage VREF is free from the influence of power supply variation, temperature variation and process variation, a current I0 (=VREF/R) flowing through the resistance R is also free from the influence of power supply variation, temperature variation and process variation, which is therefore used as a reference current.
In the conventional constant current driving circuit, PMOS transistors P22 and P23 have their gates commonly connected to the gate of the PMOS transistor P21 such that they are commonly driven by the output from the operational amplifier OP, to form a current mirror circuit together with the PMOS transistor P21. If the PMOS transistors P22 and P23 have the same element size (element parameter) as that of the PMOS transistor P21, currents I1 and I2 flowing through the respective PMOS transistors P22 and P23 become equal to the current I0. An NMOS transistor N21 is connected to the drain of the PMOS transistor P22, with its source connected to a grounding terminal VSS. This transistor has its gate and drain connected to each other (diode connection), to serve as a diode. The thus connected gate and drain of the transistor N21 are connected to the gate of an NMOS transistor N22 forming an output stage of the circuit. Thus, the NMOS transistors N21 and N22 also form a current mirror circuit, and provided that they have the same element size, a current I3 flowing through the NMOS transistor N22 becomes equal to the current I0. A switching PMOS transistor P24 and a switching NMOS transistor N23 are connected between the PMOS transistor P23 and the NMOS transistor N22, for connection to a load.
With the above arrangement, when the switching transistors P24 and N23 are driven in a complementary manner by input signals IN1 and IN2, the load is driven with a constant current. That is, when the PMOS transistor P24 is on, the load is charged from the power supply VDD via the PMOS transistors P23 and P24 with the constant current I2=I0. On the other hand, if the NMOS transistor N23 is on, the load is discharged via the NMOS transistors N22 and N23 with the constant current I3=I0.
In the conventional constant current driving circuit, when the load is charged, the PMOS transistors P23 and P24 do not have voltage drops by threshold values, and consequently an output signal at a signal output terminal OUT fully swings, i.e. the output voltage rises to a level as high as the supply voltage VDD. In recent days, however, for the economy of power consumption, it is often demanded to lower the output amplitude below the power supply voltage. To cope with such a demand, it is generally effective to provide an NMOS transistor on the side of the power supply VDD. With the NMOS transistor provided on the VDD side, when the gate of the NMOS transistor is driven with the supply voltage VDD, voltage at the source of the NMOS transistor cannot rise in excess of a value VDD-Vth (where Vth represents the gate threshold voltage of the NMOS transistor). Thus, the output at the output terminal OUT is limited on the high level side.
However, if the circuit design is changed such that the reference voltage VREF is input to the non-inverting input terminal of the operational amplifier OP and at the same time the PMOS transistors P21, P22, and P23 on the VDD side are replaced by NMOS transistors N31, N32, and N33, respectively, these NMOS transistors do not form a current mirror circuit, so that a constant current characteristic is no more obtained. More specifically, in the FIG. 1 circuit, the PMOS transistors P21, P22, and P23 have their sources connected to the power supply VDD and commonly connected such that they always have the same voltage between the gate and source (gate-source voltage) to thereby satisfy current mirror circuit conditions. On the other hand, in the FIG. 2 circuit, a reference current source circuit is formed of an operational amplifier OP, the NMOS transistor N31, and a resistance R, wherein a constant reference current I0=VREF/R is obtained by the negative feedback operation of the NMOS transistor N31. However, the NMOS transistors N32 and N33 have their drains connected to the power supply VDD side and therefore they do not have always the same voltage between the gate and source. Thus, the current mirror circuit conditions are not satisfied.
Even if the circuit is designed such that a current I1=VREF/R flows through the NMOS transistor N21 with its gate and drain connected to each other under a condition that the temperature variation and process variation each fall within a standard range, the current II and a current I2 flowing through the NMOS transistors N32 and N33 cannot always be equal to the reference current I0 flowing through the resistance R when the temperature variation and/or process variation falls out of the standard range. This is the same case as the output NMOS transistor N22 of the output stage connected to the grounding terminal VSS. That is, although the connection between the NMOS transistors N21 and N22 is the same as in the FIG. 1 circuit and therefore only a relationship of I1=I3 is satisfied, the relationship of I0=I1=I3 is not always satisfied.
As described hereinabove, according to the conventional constant current driving circuit using the PMOS current mirror circuit, the output amplitude on the high level side cannot be limited, and if the PMOS transistors forming the current mirror circuit are replaced by NMOS transistors, the circuit can be influenced by temperature variation and process variation.